In order to improve the performance of bipolar devices, extensive efforts have been made to develop new fabrication processes for producing smaller devices, spaced as close as possible, which, in turn result in both increased device density and higher switching speed (performance). The present state-of-the-art bipolar transistors capitalize on such features as extremely small and highly doped emitters, extrinsic and intrinsic base regions, self-alignment techniques to contact the emitter and base regions, to improve performance, reliability and manufacturing yields.
The emitter must be highly doped to reduce emitter resistance in order to maximize the transistor gain. The emitter must be extremely small to minimize the emitter-base capacitance. In addition to small emitter size, the transistor should have tight tolerance on that small size to facilitate better integrated circuit design. A small emitter coupled with tight tolerance results in a faster or high performance transistor.
The transistor's base area, which determines the (parasitic) base-collector capacitance, is one of the most significant parameters governing performance. In conventional bipolar transistors, where the base region is formed in a single process step, the active base is the portion of the base region directly below the emitter. The base contact is formed onto the inactive portion of the base region surrounding the emitter. In state-of-the-art bipolar devices, these two portions are formed according to two different processing steps to accommodate the need for having different dopant concentrations for both portions. The active base which is lightly doped is called the intrinsic base, while the inactive base, which is highly doped in order to reduce the base resistance, is referred to as the extrinsic base.
Self-alignment is a technique used by the semiconductor industry to reduce size and improve yields. In its absence, for example, misalignment of the emitter region with respect to the base contact can result in variations in the extrinsic base resistance. In addition, this misalignment can also result in a higher emitter-base voltage at one side of the emitter than at the other. Self-alignment techniques appear to be absolutely necessary in the integrated circuit fabrication and is often combined with the use of doped polysilicon, taking advantage of its ability to be both a dopant source (e.g., for forming the extrinsic base) and/or a conductor.
Typical of the prior art, showing polysilicon self-alignment schemes for bipolar device fabrication are those described in U.S. Pat. No. 4,507,171 issued to Bhatia et al. and assigned to the present assignee and in the article entitled "Self-Aligned Bipolar Transistor" by J. F. Shepard published in IBM Technical Disclosure Bulletin, Vol. 27, No. 2, pp. 1008-1009, July 1984. These references describe use of doped polysilicon sidewall to form a self-aligned PN junction which is then contacted by a horizontal polysilicon layer. The junction so formed is used as emitter/collector of a lateral bipolar device or as the extrinsic base contact of a vertical bipolar device.
U.S. Pat. Nos. 4,381,953 and 4,319,932, both assigned to the present assignee, disclose use of an insulator sidewall to self-align the emitter to base of a vertical bipolar transistor.
U.S. Pat. No. 4,531,282 issued to Sakai et al. describes a bipolar transistor having an extrinsic base formed from a doped polysilicon layer which also serves as self-aligned base contact encircling the emitter. An island shaped emitter is formed in the base region isolated from the base contact by an insulator extending between the periphery of the emitter and the base contact.
U.S. Pat. No. 4,338,138 issued to Cavaliere et al. and assigned to the present assignee, discloses a method of minimizing the extrinsic base area of a bipolar device to reduce the base-collector capacitance. The extrinsic base is formed by laterally diffusing dopant from a doped polysilicon layer which additionally serves as self-aligned base contact. Like in the Sakai et al. patent, the emitter is formed in the interior of the base.
U.S. patent application Ser. No. 626,279 which is assigned to the present assignee, discloses a self-aligned NPN transistor including a highly doped emitter separated on its sidewalls from the extrinsic base region by an N type guard ring shaped region having a significantly lower impurity concentration than the emitter. The guard ring is located beneath an insulating spacer.
U.S. Pat. No. 4,521,952 issued to Riseman and assigned to the present assignee discloses a method of making a vertical bipolar device having self-aligned silicide base contact. The intrinsic and extrinsic base regions are formed by ion implantation and the emitter is formed by out diffusion of dopant from a doped polysilicon layer.
U.S. Pat. No. 4,234,357 issued to Scheppele discloses use of doped polysilicon to form shallow emitters and serve as emitter contacts.
Despite the aforementioned prior art on polysilicon self-aligned bipolar transistors, there exists a need for a device in which the transistor action is confined to an extremely small area located away from the device contact regions. Since transistor action is limited to the emitter area (meaning the area of the emitter-base junction), such a device would have a small emitter, the size of which is not dependent on lithography limitations. Moreover, the small emitter size should be endowed with a tight tolerance. Another requirement of the transistor is that it have a minimal base-collector junction depth since such depth minimizes the base-collector capacitance. Yet another requirement is that the device have extremely low base and emitter contact resistances. The prior art has not been able to meet these collective requirements.
Accordingly, it is an object of the invention to provide a novel high performance bipolar transistor endowed with lithography-independent and tightly controlled submicron-wide emitter and a process for its fabrication.
In accordance with the present invention, there is provided a new and improved bipolar transistor, comprising: a first conductivity type semiconductor substrate having a portion thereof recessed below a major surface of the substrate, the recessed portion having substantially vertical walls; a multi-layer insulator-conductor-insulator formed on the substrate with the multilayer having: (1) an opening provided with substantially vertical walls exposing a portion of the substrate including the recessed portion, and (2) submicron-wide sidewall of first conductivity type material formed on the walls; an emitter of submicron depth and of a width substantially that of the sidewall formed in the substrate peripheral to the recessed portion directly underneath the sidewall, the sidewall serving as self-aligned contact to the emitter; an extrinsic base formed in the recessed portion, the base region having a conductive silicide contact recessed below the level of the emitter, the silicide contact being isolated from the emitter by an insulator formed on the walls of the recess; and an intrinsic base formed in the substrate lying directly underneath the emitter and contiguous with the extrinsic base.